Control circuit for ferroelectric gate



/0 f3 f I Nov. 2, 1965 H. T. GNUSE 3,

CONTROL CIRCUIT FOR FERROELECTRIC GATE Filed June 4, 1962 l Wizard/fizz fig 4, INVENTOR.

United States Patent 3,215,990 CONTROL CIRCUIT FOR FERROELECTRIC GATE Harmon T. Guuse, Van Nuys, Calif., assignor to Radio Corporation of America, a corporation of Delaware Filed June 4, 1962, Ser. No. 199,911 2 Claims. (Cl. 340-1732) This invention relates in general to ferroelectric control or switching circuits, useful, for example, in ferroelectric electroluminescent panel type displays.

An important application of the ferroelectric (FE) control circuits or gates is the control of the bipolar voltage (including sinusoidal alternating current voltage) applied to an electroluminescent segment. Prior art arrangements have accomplished the control of the voltage applied to such an electroluminescent segment by means of circuits employing relatively large direct-current voltages which exclude the use of transistor circuitry.

Accordingly, it is an object of this invention to provide an improved ferroelectric switching circuit.

It is another object of this invention to provide an improved control circuit for a ferroelectric gate in which the range of the control voltage is suitable for transistor circuitry.

Briefly stated, the invention comprises a pair of ferroelectric elements connected to each other at a common point. A voltage energizable output element is connected in seriesw ith the pair of ferroelectric elements. A bipolar sign-a1 voltage is applied across the series circuit and when the polarization of the ferroelectric elements is in the opposite direction of each other, the pair of ferroelectric elements presents a high impedance to the voltage source and the output element is not energized. When the pair of ferroelectric elements are polarized in the same direction the impedance presented to the source by the pair of ferroelectric elements is low and the output element is energized. A control circuit comprising a variable impedance circuit and a source of direct current voltage is connected between the common point of the pair of ferroelectric elements and a point of reference potential to polarize the ferroelectric elements in opposite directions so that the change of polarity of the energizing signal does not partially switch either ferroelectric element. The condition for blocking the energization of the output element is that the direct current voltage applied is of sufllcient amplitude to assure that the ferroelectric elements remain polarized in opposite directions throughout a complete cycle of the excitation input. Return of the direct current input to ground potential allows charge flow through the ferroelectrics to the output element.

The invention is discussed in greater detail below and is shown in the following drawings of which:

FIGURE 1 is a schematic diagram of a prior art circuit employing ferroelectric elements;

FIGURE 2 is a schematic diagram of an embodiment of the present invention;

FIGURE 3 is a graph that illustrates the required direct current voltage to eliminate charge flow for various input voltages in both the circuits shown in FIGURE 1, and FIGURE 2; and,

FIGURE 4 is a drawing of the waveform of the voltage at point A of FIGURES 1 and 2.

Throughout the figures similar reference numerals are applied to similar elements.

Referring to FIGURE 1, there is shown a ferroelectric gate 15 which comprises a pair of ferroelectric elements 11 and 12, which may be similar to the ones described in detail in J. R. Anderson, Patent No. 2,695,396, issued November 23, 1954, connected in series with each other at a common point A. An output element 13, which is shown as a capacitor in the drawings and which may be an electroluminescent segment or any other voltage energizable element, is connected in series with the pair of FE elements 11 and 12. The output element 13 is connected to a point of reference potential shown as ground.

A source of bipolar signal voltage 10, which may be a sinusoidal alternating current voltage, is applied across the series circuit comprising the FE elements 11 and 12 and the output element 13. A direct current control circuit 17 comprising a direct current voltage source, shown as a battery 14, and an isolation resistor 20, is connected between the common point A of the FE elements 11 and 12 and ground. The resistor 20 is connected between the common point A and the positive side of battery 14, which has its negative side connected to ground. The direct current voltage is used to control the conductance of the FE gate 15. The conductance of the FE gate 15 is determined by alternating current steady-state consideration in the circuit rather than by initial relative charges of FE elements 11 and 12.

Referring now to FIGURE 2, there is shown a circuit similar to that shown in FIGURE 1, except that the control circuit 19 comprises a resistor 22 and a parallel combination of a resistor 23 and a diode 25, connected in a series circuit between the common point A and the direct current voltage source 14. The diode 25 is poled so that the current flows from the battery 14 through the diode 25 and into the common point A when the voltage E of battery 14 is more positive than the voltage at point A.

In operation, referring to FIGURES 1 and 4, the direct current voltage E of battery 14 is applied between common point A and ground. The direct current voltage E controls the conductance of the FE gate 15. An energizing signal voltage V is applied by voltage source 10 across the FE elements 11 and 12, and the output element 13. The direct current voltage E polarizes FE elements 11 and 12 in diflerent directions, with respect to the energizing voltage source 10, so that elements 11 and 12 present a large impedance to the source in comparison with the impedance of element 13 during a half cycle of the excitation, and so that the FE elements 11 and 12 are clamped to a voltage -E (the value of which depends on the type of crystals used as FE elements 11 and 12) on the other half cycle. That is, E is the value of voltage at which the ferroelectric crystal switches from one direction of polarization to the other. The direct current voltage required to create this situation may be calculated.

Assuming that the voltage V is a sinusoidal alternating current voltage, the waveform at point A is shown in FIG- URE 4. The voltage -E is the clamp voltage of PE element 12. At a time after the transient switching response caused by adjustment of the direct current voltage E becomes negligible with respect to steady-state conditions, the net charge flow through the isolation resistor 20, for any complete cycle of the excitation voltage V must be zero. As long as resistor 20 provides the only direct current path into point A, no direct current component of the current flowing into point A through resistor 20 can exist. The following equation must be satisfied for the net charge passing through resistor 20 to be zero:

where V is the voltage at point A, R is the resistance of resistor 20, and E is the direct current control voltage. The equation is satisfied when the shaded area A of the waveform shown in FIGURE 4 equals the shaded area A The minimum direct current voltage E that renders FE gate completely cutofi is obtained by solving the equation above. The minimum value of E is:

where V is the peak value of the voltage at point A, and --E is the clamp voltage of FE elements 11 and 12.

The relation above shows that the cutoff voltage E is independent of the frequency of the excitation voltage V and dependent on the size and specific characteristics of the FE elements 11 and 12 only to the extent in which they atfect the clamp voltage E When a control voltage E having a magnitude larger than the magnitude of the minimum voltage E which renders FE gate 15 completely cutoff, is applied to the FE gate 15, FE elements 11 and 12 do not clamp for a full half cycle but only for a smaller portion of the half cycle. The portion of the half cycle in which FE elements 11 and 12 go into clamp depends on the relative values of the control voltage E and the excitation voltage V The FE gate 15 is rendered completely cutoff, however, since no charge is conducted to the load.

When the control voltage E has a smaller magnitude than the minimum required E to render FE gate 15 completely cutoff, the FE element 11 draws charge through resistor during the transient period and partial switching occurs. Then, in the steady-state condition, FE elements 11 and 12 have partial polarization reversals on each half cycle of the input, resulting in partial conduction of the FE gate 15.

When the control voltage E applied to the FE gate 15 is zero volts, the FE elements 11 and 12 have complete polarization reversals (the only condition is that the excitation voltage V has an amplitude that is sufficient to drive the FE elements 11 and 12 to saturation).

The direction of the current flow through resistor 20, shown in FIGURE 1, can be determined from the waveform shown in FIGURE 4. When V the voltage at point A, has a positive value larger than E the current flow will be from the battery 14 into the common point A, and when V is smaller than E (more negative) current flows through resistor 20 into the voltage source 14. Curve of FIGURE 3 shows the relationship between the required direct current voltage E to block desired values of the input voltage V As an example, 150 direct current volts are required to block an input signal having a value of 350 volts R.M.S.

The operation of the circuit shown in FIGURE 2 is in many'respects similar to the operation described for the circuit shown in FIGURE 1. However, when the voltage V has a value which is larger than the applied direct current voltage E diode 25 is non-conductive, and the resistance between common point A and the positive side of voltage source 14 is the total resistance of resistor 22 and resistor 23 in series. When the voltage V at point A is smaller than E diode 25 conducts and the total resistance of the series circuit between common point A and the voltage source 14 is approximately the resistance of resistor 22 alone.

The blocking condition of the circuit shown in FIG- URE 2, i.e., the net charge passing through resistor 22 equal to zero for the given waveform, is obtained when the area A is equal to the area A multiplied by the factor The areas A and A are defined as previously described in connection with the operation of the circuit shown in FIGURE 1, with respect to the relative values of V and E so that the condition for minimum control voltage E is (assuming that the resistance of resistor 22 is R and the resistance of resistor 23 is R n Are sin-(1st quadrant) VP V -E d6+ EB A 2 t re sm nd quadran )VA EBd6+ Are sin flst quadrant) Arc sin? (2nd quadrant) R 3 Z and respectively, in order to block an input signal of 350 volts R.M.S., approximately 50 volts direct current are required with the circuit shown in FIGURE 2, while approximately volts direct current are required with the circuit shown in FIGURE 1.

What is claimed is:

1. In combination,

a ferroelectric gate including,

a pair of ferroelectric elements connected in series with each other,

a voltage energizable output element connected to one of said ferroelectric elements,

means for applying an energizing bipolar voltage across said gate and said output element,

and control means for applying a direct current voltage to a midpoint between said ferroelectric elements to polarize said ferroelectric elements in opposite directions,

saidcontrol means including a first resistor in series with the parallel combination of a second resistor and a unidirectional conducting device.

2. A direct-current biasing circuit for controlling the flow of energy from a bipolar voltage source to an output element by controlling the conduction of current through a ferroelectric gate, said ferroelectric gate comprising a pair of ferroelectric elements serially coupled between said bipolar voltage source and said output element,

comprising in combination,

a variable impedance circuit coupled to the junction point of said ferroelectric elements in said gate,

5 6 said variable impedance circuit including a first resistor ductive when the biasing voltage has a lesser magniserially connected to the parallel combination of a tude. dlode and a second reslstor and References Cited by the Examiner means for serially applying a direct current biasing volt- UNITED STATES PATENTS age to said variable impedance circuit to polarize 5 said ferroelectric elements in opposite directions, 2,550,715 5/51 Norton 323-66 whereby the ferroelectric gate is completely cutoff when 2,900,622 8/ 59 Raichmall 34O173-2 the biasing voltage has a magnitude which cause the 3, 12 1/62 ASarS 340l73.2 X

net charge passing through said variable impedance circuit due to said bipolar voltage and said biasing 10 IRVING SRAGOW Primary Exammervoltage to be zero; and the ferroelectric gate is con- BERNARD KONICK, Examiner. 

1. IN COMBINATION A FERROELECTRIC GATE INCLUDING, A PAIR OF FERROELECTRIC ELEMENTS CONNECTED IN SERIES WITH EACH OTHER, A VOLTAGE ENERGIZABLE OUTPUT ELEMENT CONNECTED TO ONE OF SAID FERROELECTRIC ELEMENTS, MEANS FOR APPLYING AN ENERGIZING BIPOLAR VOLTAGE ACROSS SAID GATE AND SAID OUTPUT ELEMENT, AND CONTROL MEANS FOR APPLYING A DIRECT CURRENT VOLTAGE TO A MIDPOINT BETWEEN SAID FERROELECTRIC ELEMENTS TO POLARIZE SAID FERROELECTRIC ELEMENTS IN OPPOSITE DIRECTIONS, SAID CONTROL MEANS INCLUDING A FIRST RESISTOR IN SERIES WITH THE PARALLEL COMBINATION OF A SECOND RESISTOR AND A UNIDIRECTIONAL CONDUCTING DEVICE. 